专业词入口Topic Entry
RDL（Redistribution Layer，再布线层）不是把金属线“拉出去”这么简单。芯片原始焊盘、介质与金属堆栈、线宽线距、钝化开口、凸点或外部 I/O、翘曲控制和电学测试会共同决定可行性。无论是晶圆级封装、扇出型封装，还是把芯片接口转接到基板，先把交接边界讲清，才便于封装平台核对路线。An RDL is more than routing metal outward. Original pads, dielectric and metal stack, line/space, passivation openings, bumps or external I/O, warpage and electrical test jointly determine feasibility. For wafer-level, fan-out or interface-adaptation work, define the handoff before a packaging platform reviews the route.
芯片焊盘从边缘或细 pitch 区域引出、I/O 重排、晶圆级或扇出型封装原型、传感器/光电芯片转接、与中介层或 PCB 的接口匹配，以及需要在进入倒装焊前明确互连边界的项目。Pad fan-out or I/O redistribution, wafer-level or fan-out prototypes, sensor/photonic die adaptation, interposer or PCB interfaces, and projects that need an interconnect boundary before flip-chip assembly.
芯片尺寸与 pad map、I/O/pinout、焊盘金属和钝化开口、目标 I/O 坐标与 pitch、RDL 层数、介质/金属偏好或限制、最小线宽线距、凸点或焊球接口、允许热预算、翘曲边界、数量、测试方式和交付状态。未知项应标为待封装平台确认。Provide die size, pad map and pinout; pad metal and openings; target I/O coordinates and pitch; RDL layer count; dielectric/metal limits; line/space; bump interface; thermal ceiling; warpage boundary; quantity; test and delivery state.
原始焊盘氧化或钝化开口不清、金属与介质黏附不足、线宽线距超出工艺窗口、台阶覆盖不足、应力造成翘曲，或 RDL 与凸点/基板坐标定义不一致，都可能带来开路、短路、裂纹或装配失配。高密度、RF/高速、光电或扇出项目还需单独确认材料损耗、阻抗、温度和可靠性评估边界。Unclear pad/opening state, weak adhesion, out-of-window line/space, poor step coverage, stress-driven warpage or mismatched RDL/bump/carrier coordinates can cause opens, shorts, cracks or assembly mismatch. Dense, RF/high-speed, photonic and fan-out work needs separate material-loss, impedance, thermal and reliability review.
推荐下一步Next Step
请将芯片版本、原始 pad 与钝化信息、目标引出坐标、关键线宽线距、是否需要凸点、最高温度、基板或中介层接口、测试条件和样品数量放进同一份资料。素微 可协助整理为封装平台可核对的需求清单，不替代接收方的制程认证、失效分析或可靠性承诺。Put die revision, original pads and passivation, target fan-out coordinates, critical line/space, bump need, temperature ceiling, carrier/interposer interface, test conditions and quantity in one handoff. 素微 can organize a request for platform review, not replace qualification, failure analysis or reliability commitments.
提交 RDL 再布线层需求Submit RDL requestRDL 后若需要凸点、对准和贴装，应把 RDL 末端 I/O 与装配热预算一起核对。For bumping and assembly after RDL, review terminal I/O and thermal limits together.
查看倒装焊封装准备Open flip-chip guide涉及硅通孔、背面减薄或多面 I/O 时，应先把 TSV 工艺链与 RDL 的交接面拆开。For TSV, backside thinning or multi-side I/O, separate the TSV chain from the RDL interface.
查看 TSV 硅通孔工艺需求Open TSV guide先把芯片、RDL、载板和测试接口统一到一份需求里，再匹配封装资源。Unify die, RDL, carrier and test interfaces before matching a packaging resource.
查看键合与封装工艺导航Open packaging route